As integrated circuit technology continues to advance, system-level designers are finding that in many cases they can implement most or all of a particular system on a single integrated circuit. For example, numerous different functional blocks along with peripherals formerly attached to a processor at the card level are integrated onto the same die as the processor. Thus, a great deal of effort has been put into the development of system-on-chip (SoC) design methodologies, architectures, design tools, and fabrication techniques. Since SoCs are integrated circuits that combine the major functional elements of a complete end-product into a single chip using intellectual property (IP) blocks, they enable products with a broad and growing diversity of applications (e.g., communication networks, storage networks, set-top boxes, games, embedded devices, etc.) to be realized with higher performance and lower cost.
Many SoC solutions used in applications today are designed as custom integrated circuits, each with its own internal architecture and perhaps specialized software. Logical units within such an integrated circuit are often difficult to extract and reuse in different applications. Consequently, the same function is often redesigned from one application to the next. Consequently, to promote efficient SoC design and reuse, a variety of strategies are used. Since a typical SoC contains numerous functional blocks representing a very large number of logic gates, such designs can be realized through a macro-based approach targeting one or more specific hardware platforms, e.g., specific field programmable gate arrays (FPGAs), or specialized IP core libraries designed to be easily implemented in existing semiconductor fabrication processes. Macro-based design provides numerous benefits during logic entry and verification, and greatly facilitates IP reuse. From generic I/O ports to complex memory controllers and processor cores, each SoC typically uses many of these common macros.
While SoC design offers many advantages, there are still the familiar challenges of designing a complex system, now on a chip. Even with the benefit of a core library, today's SoC designers still have many options available, and making the right choices can be difficult. For example, desired hardware components have to be selected, functions have to be allocated to various hardware and software components, and optimal interconnection schemes need to be selected. All of this is performed while considering functional, performance, and cost constraints. Thus, in addition to addressing conventional integrated circuit design issues, SoC designers must also address issues traditionally handled by a system designer.
In general, system level design tools enable designers to model digital systems at levels of abstraction higher than that currently used in tool flows for digital design, e.g., register transfer level (RTL) hardware description languages (HDLs). Through successive refinements and analyses, designers use these tools to reduce the abstract system model to an actual RTL implementation. System level design tools and methods are growing in relevance to users of FPGA target systems, but to date, most of the research and development in system level design has been focused on ASIC or ASIC-like techniques for creating complex SoC designs.
Since many SoC designers rely on RTL system description and design flow tools for system implementation and analysis, a detailed design specification may be required at the outset of a design project to make important system level design determinations such as: which system functions should be implemented in hardware and which should be implemented in software, which processor core should be used, what system-wide operation constraints exist (e.g., interrupt latency, bus utilization, etc.), and can various budgets (circuit area, power consumption, etc.) be met. For example, a designer using an RTL system specification would typically need to identify all registers or memory elements, their timing conditions, and conditions under which data is transferred among them. Thus, obtaining the necessary design specification for making important system level design determinations can require almost as much effort as implementing the SoC itself.
Therefore, tools are needed to analyze higher-level representations of SoC designs early in the design process. Since rapid and accurate performance analysis is a design task that should be supported by system level design tools, it is desirable to have improved system level design tools that integrate accurate physical cost data into the system level design flow and make that data available (directly or indirectly) to designers in a useful manner. Moreover, the integration of such cost data into the design tool should not significantly hamper the designer's ability to express their system, tool speed, tool accuracy, or tool efficiency.